The present invention relates to a power MOS element and to a method for producing the same and in particular to a vertical power MOS element whose gate comprises a plurality of trenches and whose source contact and gate contact are located on the front side thereof, while the drain contact is located on the rear side thereof, in such a way that the flow of current through the element is basically perpendicular to the front side and the rear side, i.e. vertical.
Vertical power MOSFET structures have been known for quite a time. As early as in 1985 Daisuke Ueda et al. presented a power MOS element provided with a trench gate in xe2x80x9cNew Vertical Power MOSFET Structure with Extremely Reduced On-Resistancexe2x80x9d, IEEE Transactions on Electron Devices, Vol. ED-32, No. 1, January 1985. In this structure the gate is not located laterally on the surface of the wafer but vertically on the side faces of trenches plasma etched anisotropically. The element comprises a full area rear side drain contact and an upper side source contact.
In vertical power MOS transistors of this type the proportion of the channel resistance of the overall turn-on-resistance increases with a decreasing electrical strength. To decrease the power dissipation at the transistor, the chip area has to be enlarged or the channel width of the transistor has to be increased. The trench technology provides for a significantly increased channel width per active transistor area compared to the conventional DMOS technology, since in this case only technology parameters are limiting factors, and not electric parameters as in the case of the DMOS concept.
In xe2x80x9cA High-Performance Self-Aligned UMOSFET with a Vertical Trench Contact Structurexe2x80x9d by S. Matsumoto et al., IEEE Trans. Electr. Dev., Vol. 41, No. 5, May 1994, a power MOS element is disclosed which, as the sequence of layers, comprises a strongly n-doped source layer, a p-doped channel layer, a weakly n-doped drift layer and a strongly n-doped substrate layer to which the rear side drain contact is attached. Trenches filled with polysilicon, which are insulated towards the top by silicon dioxide, form the gate trenches. The source contact on the upper side of the element is connected to both the source region and to the channel region via a contact hole filled with a metal, to hold both the source region and the channel region at a same potential. By simultaneously contacting the source region and the channel region using a contact hole a space-saving circuit design can be obtained. Since in the formation of the contact hole high aspect ratios form, a metalization which can be deposited conformly must be inserted to fill the contact holes without any empty spaces. Tungsten is used for this.
In xe2x80x9cA High-Density Self-Aligned 4-Mask-Planar VDMOS Processxe2x80x9d by D. Kinzer et al., Proc.-ISPSD 96, 20 to 23 of May 1996, Maui, USA, pages 243-247, a common method for producing power MOS transistors is illustrated. For the production four masks are usually used, the first mask serving to produce an opening in a field oxide, in which the active cells are to be accomodated. The second mask is the gate mask. The third mask serves as a contact mask, the fourth, and last, mask being the metal mask. This mask separates the source metal from the gate metal. The gate contact is made directly above the active gate over the whole gate width. If this technology is applied to power elements with trench gates, a further masking is additionally necessary to produce the gate trenches. Thus, conventionally five masks are used to produce vertical power elements with gate trenches.
While Ueda, Matsumoto and Kinzer describe vertical power MOS elements which are formed on or in a semiconductor substrate doped in a layered way, Richard K. Williams et al. describe a vertical power element with locally formed p- and n-regions for forming the channel region and the source region in xe2x80x9cA 30-V P-channel Trench Gated DMOSFET with 900 xcexcxcexa9cm2 Specific On-Resistance at 2.7 Vxe2x80x9d, Proc-ISPD 96, 20 to 23 May 1996, Maui, USA, pages 53 to 57.
A full area unmasked production of the doping regions is described in WO 93/26047. A silicon carbide power MOSFET disclosed in there includes an active region and a connecting region. The connecting region serves to increase the electrical strength of the power element towards the cutting edges of it or towards the margin of the wafer in such a way that margin breakdowns at margin surfaces do not limit the power sustaining capability. The active region includes a gate trench insulating towards the drift region, the general region and the source region, which is produced by means of a well-known ion trench etching method. After an oxidation the trench is filled with polysilicon or a metal. The gate trench is contacted via a (polysilicon) gate contact, while a source contact and a drain contact are attached to the front and rear side of the element respectively. Non-contacted trenches in the margin region are provided to form potentially xe2x80x9cfloatingxe2x80x9d field plates and field rings respectively.
WO 95/09439 describes a further silicon carbide field effect element. This element includes several gate trenches which are formed in a substrate doped in a layered way. The trenches contain polysilicon as the conductive material which is insulated by means of an insulator. The substrate contains a large area source contact on the upper side and a large area drain contact on the rear side. The gate trenches are contacted by through holes in the source contact and in the insulator which surrounds the conductive material in the gate trench. Several single FET elements are connected in parallel by contacting the conductive gate electrodes by means of a metalization insulated from the source contact, which is arranged above the source contact.
The disadvantage of these well-known power MOS elements is that, after producing the source contact, in a further masking process through holes have to be formed in the source metal contact and the underlying gate insulator to be able to contact the gate electrodes in the gate trenches. If these gate trenches are to be connected in parallel to be able to process high currents, further steps for insulating the through holes towards the gate trenches and for structuring the gate electrode which are arranged above the source electrode are necessary, whereby the method for producing becomes expensive since two metalization layers being above each another are present, which have to be insulated from each other. Furthermore, the well-known power MOS element needs further steps for contacting the channel region which is usually, as is described in Ueda, set to the same potential as the source region.
The U.S. Pat. No. 5,763,915 discloses a DMOS transistor comprising a quadratically branched gate trench in which polysilicon is located which is isolated from the circumferential semiconductor material by a gate oxide. The gate trench defines squares which establish individual transistor cells, one source contact being arranged in each square, the plurality of source contacts, together with the rear side drain contact, forming a plurality of parallel-connected individual transistors which form the DMOS transistor as a whole. The quadratically branched gate trench is connected to a connection trench via a plurality of parallel gate rotors which are also formed as a trench. The source contact is realised by a continuous metal-face above the individual transistors, the source contact being in contact with the source region via through holes by an oxide. The gate contact is connected to the connection trench which is wider than the gate trench and the gate rotors via through holes.
EP-A-0 583 023 discloses a method for producing a DMOS transistor in which six masking steps are used. The DMOS transistor includes a terminating structure with several field rings, every set of adjacent field rings being isolated by an insulation trench so that the field rings can be arranged closely to one another. The field rings and the trenches are produced in the same steps as corresponding parts of the active transistor.
It is the object of the present invention to create a flexibly designable power MOS element whose production is obtained with a minimum number of steps.
In accordance with a first aspect of the present invention, this object is achieved by a power MOS element comprising: a drift region with a doping of a first doping type; a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type, and said channel region bordering on said drift region; a source region with a doping of said first doping type, said source region bordering on said channel region; a plurality of essentially parallel gate trenches spaced from one another defining an active region of said power MOS element and extending through said source region, said channel region and into said drift region, said gate trenches comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator; a connecting gate trench for connecting the gate trenches in an electrically conductive way, extending through said source region, said channel region and into said drift region, said connecting gate trench comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator, said connecting gate trench being a circumferential trench comprising a first connecting region, a second connecting region, a first longitudinal region and a second longitudinal region, said first connecting region connecting first ends of said plurality of gate trenches to one another, said second connecting region connecting second ends of said plurality of gate trenches to one another, and said first and said second longitudinal regions connecting said first and said second connecting regions to each other in such a way that the active region which is defined by said plurality of gate trenches is completely surrounded by said connecting gate trench; a source contact structure for contacting said source region; a channel contact structure for contacting said channel region; a gate contact for contacting said connecting gate trench, said gate contact being connected via a contact hole through said insulator of said connecting gate trench which is filled with an electrically conductive material to said electrically conductive material of said connecting gate trench.
In accordance with a second aspect of the present invention, this object is achieved by a power MOS element comprising: a drift region with a doping of a first doping type; a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type, and said channel region bordering on said drift region; a source region with a doping of said first doping type, said source region bordering on said channel region; a plurality of essentially parallel gate trenches spaced from one another defining an active region of the power MOS element and extending through said source region, said channel region and into said drift region, said gate trenches comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator; a connecting gate trench for connecting the gate trenches in an electrically conductive way, extending through said source region, said channel region and into said drift region, said connecting gate trench comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator, said connecting gate trench comprising a circumferential section surrounding a non-active region of said power MOS element, in which there are no gate trenches, and extension sections connected in an electrically conductive way to said circumferential section, said extension sections connecting at least a part of the gate trenches to one another in an electrically conductive way; a source contact structure for contacting said source region; a channel contact structure for contacting said channel region; a gate contact for contacting said connecting gate trench, said gate contact being connected via a contact hole through said insulator of said connecting gate trench which is filled with an electrically conductive material to said electrically conductive material of said connecting gate trench.
In accordance with a third aspect of the present invention, this object is achieved by a method for producing a power MOS element, comprising the following steps: providing a substrate having a drift region with a doping of a first doping type, a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type and said channel region bordering on said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region; photolithographic producing of essentially parallel gate trenches spaced from one another defining an active region of the power MOS element, and of a connecting gate trench by means of which said plurality of essentially parallel gate trenches is connectable to one another in an electrically conductive way in such a way that said gate trenches extend through said source region, said channel region and into said drift region, wherein said connecting gate trench being a circumferential trench comprising a first connecting region, a second connecting region, a first longitudinal region and a second longitudinal region, said first connecting region connecting first ends of said plurality of gate trenches to one another, said second connecting gate trench connecting second ends of said plurality of gate trenches to one another, and said first and said second longitudinal regions connecting said first and said second connecting regions to one another in such a way that the active region which is defined by said plurality of gate trenches is completely surrounded by said connecting gate trench; or wherein said connecting gate trench comprising a circumferential section surrounding a non-active region of said power MOS element, in which there are no gate trenches, and extension sections being connected to said circumferential section in an electrically conductive way, said extension sections connecting at least a part of said gate trenches to one another in an electrically conductive way; processing said gate trenches and said connecting gate trench in order to comprise a conductive material which is isolated from said source region, said channel region and said drift region by an insulator; photolithographic producing of contact holes for contacting said source region, said channel region and said connecting gate trench, said connecting gate trench being contactable via said contact holes associated to said connecting gate trench; filling said contact holes with an electrically conductive material; and photolithographic producing of said gate contact, said source contact and said channel contact.
The present invention is based on the recognition that one has to deviate from the usual contacting of the individual gate trenches in order to achieve a parallel connection of the individual transistors has to be dismissed. Instead of conventionally contacting each individual gate trench, a connecting gate trench is provided according to the invention, into which the individual gate trenches lead or which electrically connects the individual gate trenches to one another. The main function of this connecting gate trench is no longer to control a current through a channel but instead to connect the individual gate trenches to one another. This is why the width of this gate trench can be selected quite arbitrarily, which does not necessarily apply to the width of the active gate trenches since, in this case, electric parameters of the power MOS element are established. The width of the connecting gate trench is thus preferably selected to be larger to be able to produce contact holes in the connecting gate trench in a save and reliable way without the risk of high rejects. Via these contact holes a planar gate contact is connected to the connecting gate trench and thus to the active gate trenches by means of a contact hole filling to be able to apply a suitable gate potential to the vertical power MOS element.
The power MOS element as a whole according to the invention can be produced using three photolithographic steps only. No extra mask is needed for doping local p- or n-regions. Instead a substrate with a drift region, a channel region and a source region is used, the three regions forming a layered arrangement. The first photolithographic step serves to produce a plurality of gate trenches and the connecting gate trench. Preferably a terminating structure can also be defined in the step, which either comprises several floating trenches disposed around the active region or, in analogy to a field plate structure, includes a trench section short-circuited with the source region and the drain region.
The second photolithographic step serves to produce the contact holes for contacting the source region and the channel region and for contacting the connecting gate trench. It is pointed out that the active gate trenches are not contacted externally but solely by means of the connecting gate trench. Finally the third photolithographic step serves to structure the metal contacts in such a way that a large area source contact is provided which covers substantially the whole power MOS element except for a region above the connecting gate trench where the planar gate contact is located. If special margin structures are provided, a source contact is not present via these either.
Preferably the connecting gate trench is a closed trench arranged around the active region, which contacts the active gate trenches at both ends of the same to be able to feed the gate potential at both ends of the gate trenches. This arrangement has the advantage that a termination of the active region within the cutting edge of the power MOS element is obtained at this stage already, the limitation, with drain source voltages, which are not too large, at the power MOS element, being sufficient to avoid margin breakdowns. Thus, any kind of special margin termination can be dispensed with at lower voltage classes, whereby costs can be saved, a fact which is of special importance in mass markets, such as the automobile industry or the consumer area.
The contacting of the gate trenches via an extra connecting gate trench thus enables, without additional technology steps, placing the physical gate contacts as required by the user, either at the margin of the power MOS element or in the middle of the power MOS element or in general at any place, since placing the gate contact is decoupled from the location of the active gate trenches by the connecting gate trench.